Phased Logic Design

Phased Logic is a logic family and synthesis methodology that creates a self-timed design directly from the netlist of a clocked design. Phased Logic designs are delay insensitive to wire delays between phased logic gates and have no global signals other than a power-on reset. Because the starting point is a clocked netlist, any HDL/logic synthesis tool can be used to create the clocked netlist. We have a freely available distribution that allows you to create and simulate your own phased logic designs.

Current funding is provided by the NSF, Award #0098272

Past Projects

Past projects have involved VHDL model development for programmable logic and memory, standard cell library development and characterization, and WWW-based CAD tool access.